The present invention relates to a semiconductor device, a circuit board, an electronic instrument, and a method of manufacturing a semiconductor device. More particularly, the present invention relates to a semiconductor device having a configuration suitable for a three-dimensional stacking technology.
In order to reduce the size and weight of a portable electronic instrument such as a portable telephone, a notebook-type personal computer or a personal data assistant (PDA), various electronic parts such as a semiconductor chip provided in the electronic instrument have been reduced in size. Moreover, the space for mounting the electronic parts is extremely limited. Therefore, the package form of the semiconductor chip has been developed, and an extremely small package called a chip scale package (CSP) has been proposed.
Since the mounting area of the semiconductor chip manufactured by using the CSP technology is approximately equal to the area of the semiconductor chip, high-density mounting can be achieved.
However, since the electronic instrument is expected to be further reduced in size and increased in function in the future, it is necessary to increase the mounting density of the semiconductor chip.
In view of the above situation, a three-dimensional stacking technology as disclosed in Japanese Patent Application Laid-open No. 2002-50738 has been proposed. This three-dimensional stacking technology achieves high-density mounting of semiconductor chips by stacking semiconductor chips having the same function or by stacking semiconductor chips having different functions, and interconnecting the semiconductor chips.
In the above-described three-dimensional stacking technology, the technology of interconnecting the semiconductor chips is very important. In order to allow the semiconductor device including a plurality of semiconductor chips to exhibit expected functions, interconnects must be formed conforming to the design, and reliability of the semiconductor device must be secured by securing the connection between the semiconductor chips.
A semiconductor chip used for the three-dimensional stacking technology has an electrode structure in which electrodes are formed on the upper and back surfaces of the semiconductor substrate, a through-hole is formed through the upper and back surfaces of the semiconductor substrate, and the upper and lower electrodes are electrically connected through the through-hole. The electrode formed on the back surface of one semiconductor chip is connected with the electrode formed on the upper surface of another semiconductor chip by stacking the semiconductor chips having such an electrode structure, whereby the semiconductor chips are interconnected.
In such a semiconductor device, the connection state, that is, the electrical connection state between the electrodes, is an important factor in securing reliability of the semiconductor device. In the case where an electrical connection failure occurs, malfunction may occur in the semiconductor device.
On the other hand, since a number of steps are necessary for forming the above-described electrode structure, manufacturing efficiency is decreased. It is indispensable to form the through-hole in the above-described electrode structure. However, the degrees of freedom of design of the semiconductor chip may be limited depending on the formation position of the through-hole. Therefore, it is necessary to form an electrode structure taking the degrees of freedom of design into consideration.